1. Field of Invention
The present invention relates to a wafer scale process for attaching a semiconductor light emitting device to a support substrate.
2. Description of Related Art
Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. Typically, III-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, III-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p-type regions.
FIG. 10 illustrates a light emitting diode die 110 attached to a submount 114, described in more detail in U.S. Pat. No. 6,876,008. Electrical connections between the solderable surfaces on the top and bottom surfaces of the submount are formed within the submount. The solderable areas on the top of the submount, on which solder balls 122-1 and 122-2 are disposed, are electrically connected to the solderable areas on the bottom of the submount, which attach to solder joint 138, by a conductive path within the submount. Solder joint 138 electrically connects solderable areas on the bottom of the submount to a board 134. Submount 114 may be, for example, a silicon/glass composite submount with several different regions. Silicon regions 114-2 are surrounded by metalizations 118-1 and 118-2, which form the conductive path between the top surface and the bottom surface of the submount. Circuitry such as ESD protection circuitry may be formed in the silicon regions 114-2 surrounded by metalizations 118-1 and 118-2, or in other silicon region 114-3. Such other silicon 114-3 regions may also electrically contact the die 110 or the board 134. Glass regions 114-1 electrically isolate different regions of silicon. Solder joints 138 may be electrically isolated by an insulating region 135 which may be, for example, a dielectric layer or air.
In the device illustrated in FIG. 10, the submount 114 including metalizations 118-1 and 118-2 is formed separately from die 110, before die 110 is attached to submount 114. For example, U.S. Pat. No. 6,876,008 explains that a silicon wafer, which is comprised of sites for many submounts, is grown to include any desired circuitry such as the ESD protection circuitry mentioned above. Holes are formed in the wafer by conventional masking and etching steps. A conductive layer such as a metal is formed over the wafer and in the holes. The conductive layer may then be patterned. A layer of glass is then formed over the wafer and in the holes. Portions of the glass layer and wafer are removed to expose the conductive layer. The conductive layer on the underside of the wafer may then be patterned and additional conductive layers may be added and patterned. Once the underside of the wafer is patterned, individual LED dice 110 may be physically and electrically connected to the conductive regions on the submount by interconnects 122. In other words, the LEDs 110 are attached to the submount 114 after being diced into individual diodes.